#ifndef INCLUDED_CYFITTER_H
#define INCLUDED_CYFITTER_H
#include <cydevice.h>
#include <cydevice_trm.h>

/* Counter_1_CounterUDB */
#define Counter_1_CounterUDB_sC8_counterdp_u0__16BIT_A0_REG CYREG_B0_UDB05_06_A0
#define Counter_1_CounterUDB_sC8_counterdp_u0__16BIT_A1_REG CYREG_B0_UDB05_06_A1
#define Counter_1_CounterUDB_sC8_counterdp_u0__16BIT_D0_REG CYREG_B0_UDB05_06_D0
#define Counter_1_CounterUDB_sC8_counterdp_u0__16BIT_D1_REG CYREG_B0_UDB05_06_D1
#define Counter_1_CounterUDB_sC8_counterdp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
#define Counter_1_CounterUDB_sC8_counterdp_u0__16BIT_F0_REG CYREG_B0_UDB05_06_F0
#define Counter_1_CounterUDB_sC8_counterdp_u0__16BIT_F1_REG CYREG_B0_UDB05_06_F1
#define Counter_1_CounterUDB_sC8_counterdp_u0__A0_A1_REG CYREG_B0_UDB05_A0_A1
#define Counter_1_CounterUDB_sC8_counterdp_u0__A0_REG CYREG_B0_UDB05_A0
#define Counter_1_CounterUDB_sC8_counterdp_u0__A1_REG CYREG_B0_UDB05_A1
#define Counter_1_CounterUDB_sC8_counterdp_u0__D0_D1_REG CYREG_B0_UDB05_D0_D1
#define Counter_1_CounterUDB_sC8_counterdp_u0__D0_REG CYREG_B0_UDB05_D0
#define Counter_1_CounterUDB_sC8_counterdp_u0__D1_REG CYREG_B0_UDB05_D1
#define Counter_1_CounterUDB_sC8_counterdp_u0__DP_AUX_CTL_REG CYREG_B0_UDB05_ACTL
#define Counter_1_CounterUDB_sC8_counterdp_u0__F0_F1_REG CYREG_B0_UDB05_F0_F1
#define Counter_1_CounterUDB_sC8_counterdp_u0__F0_REG CYREG_B0_UDB05_F0
#define Counter_1_CounterUDB_sC8_counterdp_u0__F1_REG CYREG_B0_UDB05_F1
#define Counter_1_CounterUDB_sC8_counterdp_u0__MSK_DP_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
#define Counter_1_CounterUDB_sC8_counterdp_u0__PER_DP_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
#define Counter_1_CounterUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
#define Counter_1_CounterUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL
#define Counter_1_CounterUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL
#define Counter_1_CounterUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL
#define Counter_1_CounterUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL
#define Counter_1_CounterUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK
#define Counter_1_CounterUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK
#define Counter_1_CounterUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK
#define Counter_1_CounterUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK
#define Counter_1_CounterUDB_sCTRLReg_SyncCtl_ctrlreg__7__MASK 0x80u
#define Counter_1_CounterUDB_sCTRLReg_SyncCtl_ctrlreg__7__POS 7
#define Counter_1_CounterUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL
#define Counter_1_CounterUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_REG CYREG_B0_UDB05_CTL
#define Counter_1_CounterUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL
#define Counter_1_CounterUDB_sCTRLReg_SyncCtl_ctrlreg__COUNT_REG CYREG_B0_UDB05_CTL
#define Counter_1_CounterUDB_sCTRLReg_SyncCtl_ctrlreg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL
#define Counter_1_CounterUDB_sCTRLReg_SyncCtl_ctrlreg__MASK 0x80u
#define Counter_1_CounterUDB_sCTRLReg_SyncCtl_ctrlreg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
#define Counter_1_CounterUDB_sCTRLReg_SyncCtl_ctrlreg__PERIOD_REG CYREG_B0_UDB05_MSK
#define Counter_1_CounterUDB_sCTRLReg_SyncCtl_ctrlreg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
#define Counter_1_CounterUDB_sSTSReg_rstSts_stsreg__0__MASK 0x01u
#define Counter_1_CounterUDB_sSTSReg_rstSts_stsreg__0__POS 0
#define Counter_1_CounterUDB_sSTSReg_rstSts_stsreg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
#define Counter_1_CounterUDB_sSTSReg_rstSts_stsreg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST
#define Counter_1_CounterUDB_sSTSReg_rstSts_stsreg__1__MASK 0x02u
#define Counter_1_CounterUDB_sSTSReg_rstSts_stsreg__1__POS 1
#define Counter_1_CounterUDB_sSTSReg_rstSts_stsreg__3__MASK 0x08u
#define Counter_1_CounterUDB_sSTSReg_rstSts_stsreg__3__POS 3
#define Counter_1_CounterUDB_sSTSReg_rstSts_stsreg__5__MASK 0x20u
#define Counter_1_CounterUDB_sSTSReg_rstSts_stsreg__5__POS 5
#define Counter_1_CounterUDB_sSTSReg_rstSts_stsreg__6__MASK 0x40u
#define Counter_1_CounterUDB_sSTSReg_rstSts_stsreg__6__POS 6
#define Counter_1_CounterUDB_sSTSReg_rstSts_stsreg__MASK 0x6Bu
#define Counter_1_CounterUDB_sSTSReg_rstSts_stsreg__MASK_REG CYREG_B0_UDB05_MSK
#define Counter_1_CounterUDB_sSTSReg_rstSts_stsreg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
#define Counter_1_CounterUDB_sSTSReg_rstSts_stsreg__PER_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
#define Counter_1_CounterUDB_sSTSReg_rstSts_stsreg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL
#define Counter_1_CounterUDB_sSTSReg_rstSts_stsreg__STATUS_CNT_REG CYREG_B0_UDB05_ST_CTL
#define Counter_1_CounterUDB_sSTSReg_rstSts_stsreg__STATUS_CONTROL_REG CYREG_B0_UDB05_ST_CTL
#define Counter_1_CounterUDB_sSTSReg_rstSts_stsreg__STATUS_REG CYREG_B0_UDB05_ST

/* CharLCD_1_LCDPort */
#define CharLCD_1_LCDPort__0__MASK 0x01u
#define CharLCD_1_LCDPort__0__PC CYREG_PRT2_PC0
#define CharLCD_1_LCDPort__0__PORT 2u
#define CharLCD_1_LCDPort__0__SHIFT 0
#define CharLCD_1_LCDPort__1__MASK 0x02u
#define CharLCD_1_LCDPort__1__PC CYREG_PRT2_PC1
#define CharLCD_1_LCDPort__1__PORT 2u
#define CharLCD_1_LCDPort__1__SHIFT 1
#define CharLCD_1_LCDPort__2__MASK 0x04u
#define CharLCD_1_LCDPort__2__PC CYREG_PRT2_PC2
#define CharLCD_1_LCDPort__2__PORT 2u
#define CharLCD_1_LCDPort__2__SHIFT 2
#define CharLCD_1_LCDPort__3__MASK 0x08u
#define CharLCD_1_LCDPort__3__PC CYREG_PRT2_PC3
#define CharLCD_1_LCDPort__3__PORT 2u
#define CharLCD_1_LCDPort__3__SHIFT 3
#define CharLCD_1_LCDPort__4__MASK 0x10u
#define CharLCD_1_LCDPort__4__PC CYREG_PRT2_PC4
#define CharLCD_1_LCDPort__4__PORT 2u
#define CharLCD_1_LCDPort__4__SHIFT 4
#define CharLCD_1_LCDPort__5__MASK 0x20u
#define CharLCD_1_LCDPort__5__PC CYREG_PRT2_PC5
#define CharLCD_1_LCDPort__5__PORT 2u
#define CharLCD_1_LCDPort__5__SHIFT 5
#define CharLCD_1_LCDPort__6__MASK 0x40u
#define CharLCD_1_LCDPort__6__PC CYREG_PRT2_PC6
#define CharLCD_1_LCDPort__6__PORT 2u
#define CharLCD_1_LCDPort__6__SHIFT 6
#define CharLCD_1_LCDPort__AG CYREG_PRT2_AG
#define CharLCD_1_LCDPort__AMUX CYREG_PRT2_AMUX
#define CharLCD_1_LCDPort__BIE CYREG_PRT2_BIE
#define CharLCD_1_LCDPort__BIT_MASK CYREG_PRT2_BIT_MASK
#define CharLCD_1_LCDPort__BYP CYREG_PRT2_BYP
#define CharLCD_1_LCDPort__CTL CYREG_PRT2_CTL
#define CharLCD_1_LCDPort__DM0 CYREG_PRT2_DM0
#define CharLCD_1_LCDPort__DM1 CYREG_PRT2_DM1
#define CharLCD_1_LCDPort__DM2 CYREG_PRT2_DM2
#define CharLCD_1_LCDPort__DR CYREG_PRT2_DR
#define CharLCD_1_LCDPort__INP_DIS CYREG_PRT2_INP_DIS
#define CharLCD_1_LCDPort__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
#define CharLCD_1_LCDPort__LCD_EN CYREG_PRT2_LCD_EN
#define CharLCD_1_LCDPort__MASK 0x7Fu
#define CharLCD_1_LCDPort__PORT 2u
#define CharLCD_1_LCDPort__PRT CYREG_PRT2_PRT
#define CharLCD_1_LCDPort__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
#define CharLCD_1_LCDPort__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
#define CharLCD_1_LCDPort__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
#define CharLCD_1_LCDPort__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
#define CharLCD_1_LCDPort__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
#define CharLCD_1_LCDPort__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
#define CharLCD_1_LCDPort__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
#define CharLCD_1_LCDPort__PS CYREG_PRT2_PS
#define CharLCD_1_LCDPort__SHIFT 0
#define CharLCD_1_LCDPort__SLW CYREG_PRT2_SLW

/* CounterISR */
#define CounterISR__ES2_PATCH 0u
#define CounterISR__INTC_CLR_EN_REG CYREG_INTC_CLR_EN0
#define CounterISR__INTC_CLR_PD_REG CYREG_INTC_CLR_PD0
#define CounterISR__INTC_MASK 0x01u
#define CounterISR__INTC_NUMBER 0u
#define CounterISR__INTC_PRIOR_NUM 7u
#define CounterISR__INTC_PRIOR_REG CYREG_INTC_PRIOR0
#define CounterISR__INTC_SET_EN_REG CYREG_INTC_SET_EN0
#define CounterISR__INTC_SET_PD_REG CYREG_INTC_SET_PD0
#define CounterISR__INTC_VECT (CYREG_INTC_VECT_MBASE+0x00u)

/* clock_1 */
#define clock_1__CFG0 CYREG_CLKDIST_DCFG0_CFG0
#define clock_1__CFG1 CYREG_CLKDIST_DCFG0_CFG1
#define clock_1__CFG2 CYREG_CLKDIST_DCFG0_CFG2
#define clock_1__CFG2_SRC_SEL_MASK 0x07u
#define clock_1__INDEX 0x00u
#define clock_1__PM_ACT_CFG CYREG_PM_ACT_CFG2
#define clock_1__PM_ACT_MSK 0x01u
#define clock_1__PM_STBY_CFG CYREG_PM_STBY_CFG2
#define clock_1__PM_STBY_MSK 0x01u

/* P0_4 */
#define P0_4__0__MASK 0x10u
#define P0_4__0__PC CYREG_PRT0_PC4
#define P0_4__0__PORT 0u
#define P0_4__0__SHIFT 4
#define P0_4__AG CYREG_PRT0_AG
#define P0_4__AMUX CYREG_PRT0_AMUX
#define P0_4__BIE CYREG_PRT0_BIE
#define P0_4__BIT_MASK CYREG_PRT0_BIT_MASK
#define P0_4__BYP CYREG_PRT0_BYP
#define P0_4__CTL CYREG_PRT0_CTL
#define P0_4__DM0 CYREG_PRT0_DM0
#define P0_4__DM1 CYREG_PRT0_DM1
#define P0_4__DM2 CYREG_PRT0_DM2
#define P0_4__DR CYREG_PRT0_DR
#define P0_4__INP_DIS CYREG_PRT0_INP_DIS
#define P0_4__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
#define P0_4__LCD_EN CYREG_PRT0_LCD_EN
#define P0_4__MASK 0x10u
#define P0_4__PORT 0u
#define P0_4__PRT CYREG_PRT0_PRT
#define P0_4__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
#define P0_4__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
#define P0_4__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
#define P0_4__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
#define P0_4__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
#define P0_4__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
#define P0_4__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
#define P0_4__PS CYREG_PRT0_PS
#define P0_4__SHIFT 4
#define P0_4__SLW CYREG_PRT0_SLW

/* P0_5 */
#define P0_5__0__MASK 0x20u
#define P0_5__0__PC CYREG_PRT0_PC5
#define P0_5__0__PORT 0u
#define P0_5__0__SHIFT 5
#define P0_5__AG CYREG_PRT0_AG
#define P0_5__AMUX CYREG_PRT0_AMUX
#define P0_5__BIE CYREG_PRT0_BIE
#define P0_5__BIT_MASK CYREG_PRT0_BIT_MASK
#define P0_5__BYP CYREG_PRT0_BYP
#define P0_5__CTL CYREG_PRT0_CTL
#define P0_5__DM0 CYREG_PRT0_DM0
#define P0_5__DM1 CYREG_PRT0_DM1
#define P0_5__DM2 CYREG_PRT0_DM2
#define P0_5__DR CYREG_PRT0_DR
#define P0_5__INP_DIS CYREG_PRT0_INP_DIS
#define P0_5__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
#define P0_5__LCD_EN CYREG_PRT0_LCD_EN
#define P0_5__MASK 0x20u
#define P0_5__PORT 0u
#define P0_5__PRT CYREG_PRT0_PRT
#define P0_5__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
#define P0_5__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
#define P0_5__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
#define P0_5__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
#define P0_5__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
#define P0_5__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
#define P0_5__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
#define P0_5__PS CYREG_PRT0_PS
#define P0_5__SHIFT 5
#define P0_5__SLW CYREG_PRT0_SLW

/* Miscellaneous */
/* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release */
#define CYDEV_DEBUGGING_DPS_SWD_SWV 6
#define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0
#define CYDEV_CONFIGURATION_MODE_DMA 2
#define CYDEV_CONFIG_FASTBOOT_ENABLED 1
#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u
#define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u
#define CYDEV_CHIP_MEMBER_3A 1u
#define CYDEV_CHIP_FAMILY_PSOC3 1u
#define CYDEV_CHIP_DIE_LEOPARD 1u
#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_DIE_LEOPARD
#define BCLK__BUS_CLK__HZ 24000000U
#define BCLK__BUS_CLK__KHZ 24000U
#define BCLK__BUS_CLK__MHZ 24U
#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT
#define CYDEV_CHIP_DIE_PANTHER 3u
#define CYDEV_CHIP_DIE_PSOC4A 2u
#define CYDEV_CHIP_DIE_PSOC5LP 4u
#define CYDEV_CHIP_DIE_UNKNOWN 0u
#define CYDEV_CHIP_FAMILY_PSOC4 2u
#define CYDEV_CHIP_FAMILY_PSOC5 3u
#define CYDEV_CHIP_FAMILY_UNKNOWN 0u
#define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC3
#define CYDEV_CHIP_JTAG_ID 0x1E028069u
#define CYDEV_CHIP_MEMBER_4A 2u
#define CYDEV_CHIP_MEMBER_5A 3u
#define CYDEV_CHIP_MEMBER_5B 4u
#define CYDEV_CHIP_MEMBER_UNKNOWN 0u
#define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_3A
#define CYDEV_CHIP_REVISION_3A_ES1 0u
#define CYDEV_CHIP_REVISION_3A_ES2 1u
#define CYDEV_CHIP_REVISION_3A_ES3 3u
#define CYDEV_CHIP_REVISION_4A_ES0 17u
#define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u
#define CYDEV_CHIP_REVISION_5A_ES0 0u
#define CYDEV_CHIP_REVISION_5A_ES1 1u
#define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u
#define CYDEV_CHIP_REVISION_5B_ES0 0u
#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_USED CYDEV_CHIP_REVISION_3A_PRODUCTION
#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REV_LEOPARD_PRODUCTION
#define CYDEV_CHIP_REV_LEOPARD_ES1 0u
#define CYDEV_CHIP_REV_LEOPARD_ES2 1u
#define CYDEV_CHIP_REV_LEOPARD_ES3 3u
#define CYDEV_CHIP_REV_PANTHER_ES0 0u
#define CYDEV_CHIP_REV_PANTHER_ES1 1u
#define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1u
#define CYDEV_CHIP_REV_PSOC4A_ES0 17u
#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u
#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u
#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u
#define CYDEV_CONFIGURATION_CLEAR_SRAM 1
#define CYDEV_CONFIGURATION_COMPRESSED 0
#define CYDEV_CONFIGURATION_DMA 1
#define CYDEV_CONFIGURATION_ECC 1
#define CYDEV_CONFIGURATION_IMOENABLED CYDEV_CONFIG_FASTBOOT_ENABLED
#define CYDEV_CONFIGURATION_MODE CYDEV_CONFIGURATION_MODE_DMA
#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0
#define CYDEV_CONFIGURATION_MODE_UNCOMPRESSED 1
#define CYDEV_CONFIG_UNUSED_IO CYDEV_CONFIG_UNUSED_IO_AllowButWarn
#define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1
#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2
#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD_SWV
#define CYDEV_DEBUGGING_DPS_Disable 3
#define CYDEV_DEBUGGING_DPS_JTAG_4 1
#define CYDEV_DEBUGGING_DPS_JTAG_5 0
#define CYDEV_DEBUGGING_DPS_SWD 2
#define CYDEV_DEBUGGING_ENABLE 1
#define CYDEV_DEBUGGING_REQXRES 1
#define CYDEV_DEBUGGING_XRES 0
#define CYDEV_DEBUG_ENABLE_MASK 0x01u
#define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DEBUG
#define CYDEV_DMA_CHANNELS_AVAILABLE 24u
#define CYDEV_ECC_ENABLE 0
#define CYDEV_INSTRUCT_CACHE_ENABLED 0
#define CYDEV_INTR_RISING 0x00000001u
#define CYDEV_PROJ_TYPE 0
#define CYDEV_PROJ_TYPE_BOOTLOADER 1
#define CYDEV_PROJ_TYPE_LOADABLE 2
#define CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER 3
#define CYDEV_PROJ_TYPE_STANDARD 0
#define CYDEV_PROTECTION_ENABLE 0
#define CYDEV_VARIABLE_VDDA 0
#define CYDEV_VDDA 5.0
#define CYDEV_VDDA_MV 5000
#define CYDEV_VDDD 5.0
#define CYDEV_VDDD_MV 5000
#define CYDEV_VDDIO0 5.0
#define CYDEV_VDDIO0_MV 5000
#define CYDEV_VDDIO1 5.0
#define CYDEV_VDDIO1_MV 5000
#define CYDEV_VDDIO2 5.0
#define CYDEV_VDDIO2_MV 5000
#define CYDEV_VDDIO3 5.0
#define CYDEV_VDDIO3_MV 5000
#define CYDEV_VIO0 5
#define CYDEV_VIO0_MV 5000
#define CYDEV_VIO1 5
#define CYDEV_VIO1_MV 5000
#define CYDEV_VIO2 5
#define CYDEV_VIO2_MV 5000
#define CYDEV_VIO3 5
#define CYDEV_VIO3_MV 5000
#define DMA_CHANNELS_USED__MASK0 0x00000000u
#define CYDEV_BOOTLOADER_ENABLE 0

#endif /* INCLUDED_CYFITTER_H */
